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You can get the free status update report for this canadian trademark. Click here. McCabe, Jr from IPethicslaw. Ask a Lawyer Question: Please enter your question. Ask A Question. Each of unit pixels includes a transistor with multi gates, wherein transistors of at least two unit pixels of the R, G, and B unit pixels include offset regions having different resistance values between the multi gates from one another.
The unit pixels having different resistance values from one another include light-emitting devices, respectively, and the transistors for controlling currents supplied to the light-emitting devices of each unit pixel have channel layers with the same size.
The R, G, and B unit pixels further include light-emitting devices driven by the transistors, respectively, Resistance values of the offset regions of the transistors are determined by the luminous efficiencies of the light-emitting devices driven by the transistors. A resistance value of an offset region of a transistor for driving a light-emitting device having the highest luminous efficiency among the transistors of the R, G, and B unit pixels is higher than those of transistors for driving light-emitting devices having relatively low luminous efficiency.
The offset regions of the transistors of the R, G, and B unit pixels have different doping concentrations from one another. The R, G, and B unit pixels further include light-emitting devices driven by the transistors, respectively, where an offset region of a transistor for driving a light emitting device having the highest luminous efficiency among the transistors is doped with an impurity concentration lower than the offset regions of transistors for driving light-emitting devices having relatively low luminous efficiency.
The offset regions of at least two transistors among the transistors of the R, G, and B unit pixels are doped with impurities having different doping concentrations from one another.
The R, G, and B unit pixels further include light-emitting devices driven by the transistors, respectively, where an offset region of a transistor for driving a light-emitting device having the highest luminous efficiency of the at least two transistors is doped with impurities at a doping concentration lower than that of the other transistor. The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail preferred embodiments thereof with reference to the attached drawings in which:.
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein.
Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
In the drawings, the thickness of layers and regions may be exaggerated for clarity. Like numbers refer to like elements throughout the specification. Referring to FIGS. The gate electrode includes multi gates and corresponding to the semiconductor layer In addition, the semiconductor layer further includes an offset region between the multi gates and , i. In FIG. In other words, the mask is used as a mask for ion implanting of impurities into the portion of the offset region , and the offset length L roff is determined in accordance with an overlapping degree between the mask and the offset region In other words, the mask is used as a mask for ion implanting of impurities into the portion of the offset region , and the offset length L goff is determined in accordance with an overlapping degree between the mask and the offset region In the driving transistor of the G unit pixel having the highest luminous efficiency among the R, G, and B unit pixels, the offset length L goff in the offset region between the multi gates and is made longer than the offset length L roff in the offset region between the multi gates and of the driving transistor of the R unit pixel having low luminous efficiency.
And the length L boff of the offset portion among the length L b of the offset region is zero. As mentioned above, in the driving transistor of the G unit pixel having the highest luminous efficiency among the R, G, and B unit pixels the offset length L goff in the offset region between the multi gates and , is made longer than the offset length L roff in the offset region between the multi gates and of the driving transistor of the R unit pixel having relatively low luminous efficiency, and the offset region between the multi gates and of the driving transistor of the B unit pixel having the lowest luminous efficiency is entirely doped with impurities to make the length L boff zero, so that resistance values of the offset regions between the multi gates of the R, G, and B unit pixels are made different from one another, thereby embodying the white balance.
According to an embodiment of the present invention, offset regions between multi gates of each driving transistor of R, G, and B unit pixels may be formed to have different structures from one another, so that resistance values of the offset regions are adjusted, thereby embodying the white balance.
In other words, lengths L r , L g and L b of offset regions between multi gates of R, G, and B unit pixels each having different luminous efficiency from one another are formed to be the same, and lengths L roff , L goff and L boff of the offset portions not doped with impurities in the offset regions , and are formed to be different from one another, so that resistance values of the offset regions between the multi gates of the R, G, and B unit pixels are made different with one another, thereby embodying the white balance.
That is, the G unit pixel having the highest luminous efficiency may be formed to have the highest resistance value by making the offset length longest in the offset region Meanwhile, the B unit pixel having the lowest luminous efficiency may be formed to have the lowest resistance value by entirely doping the offset region and making the offset length in the offset region zero.
The offset region of the R unit pixel having the luminous efficiency between those of the G unit pixel and the B unit pixel may be formed to have the offset length L roff shorter than the offset length L goff of the offset region of the G unit pixel, so that the R unit pixel has a resistance value between those of the G unit pixel and the B unit pixel.
Although the multi gates include two gates in various embodiments of the present invention, it is also possible to have a structure that has different resistance values of R, G, and B unit pixels from one another by making offset regions between multi gates of driving transistors of the R, G, and B unit pixels have different geometric structures from one another regardless of the number of gates and structures of the multi gates.
For example, by making the total length of the offset regions between the multi gates of the R, G, and B unit pixels constant and forming the offset regions to have different widths from one another, the offset regions of the R, G, and B unit pixels can be formed to have different resistance values from one another.
In addition, by making widths of the offset regions between the multi gates of the R, G, and B unit pixels have the same value and adjusting the total lengths of the offset regions to be different, the offset regions of the R, G, and B unit pixels can be also formed to have different resistance values from one another.
Furthermore, according to another embodiment of the present invention, by adjusting sizes of the offset regions between the multi gates of the R, G, and B unit pixels while adjusting lengths of offset portions not doped with impurities in the offset regions of the R, G, and B unit pixels at the same time, resistance values of the offset regions between the multi gates are adjusted, so that the white balance can be embodied.
Referring to FIG. In addition, the semiconductor layer further includes an offset region formed between the multi gates and , i. The semiconductor layer further includes an offset region formed between the multi gates and , i. The offset region is an intrinsic region not doped with impurities. Thus, in the G unit pixel having the highest luminous efficiency, the offset region between the multi gates and has no impurities doped, so that it has a resistance value higher than that of the offset region of the R unit pixel doped with a relatively low impurity concentration.
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